
M82510
8. CLCFDCLOCKS CONFIGURE REGISTER
CLCFDClocks Configure Register
271072–21
This register defines the Transmit and Receive Code
modes and sources.
RxCMDRx Clock ModeD
This bit selects the mode
of the receive clock which is used to sample the
received data.
0D 16X Mode.
1D 1X Mode. In this mode the receive data must be
synchronous to the Rx Clock; supplied via the
SCLK pin.
RxCSDRx Clock SourceD
This bit selects the
source of the internal receive clock in the case of
16X mode (as programmed by the RxCM bit above).
0DBRGB Output
1DBRGA Output
TxCMDTransmit Clock ModeD
This bit selects the
mode of the Transmit Data Clock, which is used to
clock out the Transmit Data.
0D 16X Mode
1D 1X Mode. In this mode the Transmit data is
synchronous to the Serial Clock; supplied via
the SCLK pin.
TxCSDTransmit
source of internal Transmit Clock in case of 16X
mode.
Clock
SourceD
Selects
the
0DBRGB Output.
1DBRGA Output.
9. BACFDBRGA CONFIGURATION REGISTER
BACFDBRGA Configuration Register
271072–22
This register defines the BRGA clock sources and
the mode of operation.
BACSDBRGA Clock SourceD
Selects the input
clock source for Baud Rate Generator A.
0DSystem Clock
1DSCLK Pin
This bit has no effect if BRGA is configured as a
timer.
BAMDBRGA Mode of OperationD
Selects be-
tween the Timer mode or the Baud Rate Generator
Mode.
0D Timer Mode (in this mode the input clock
source is always the system clock).
1D Baud Rate Generator Mode
22