
M82510
4. FMDDFIFO MODE REGISTER
FMDDFIFO Mode Register
271072–17
This register configures the Tx and Rx FIFO’s
threshold levelsDthe occupancy levels that can
cause an interrupt.
7D6DReserved
RFT1DRFT0DReceive FIFO ThresholdD
When
the Rx FIFO occupancy is greater than the level indi-
cated by these bits the Rx FIFO Interrupt is activat-
ed.
3D2DReserved
TFT1DTFT0DTransmit FIFO ThresholdD
When
the TX FIFO occupancy is less than or equal to the
level indicated by these bits the Tx FIFO Interrupt is
activated.
5. ACR0DADDRESS/CONTROL CHARACTER REGISTER 0
ARC0DAddress/Control Character Register 0
271072–18
This register contains a byte which is compared to
each received character. The exact function de-
pends on the configuration of the IMD register.
In normal mode this register may be used to pro-
gram a special control character; a matched charac-
ter will be reported in the RECEIVE STATUS regis-
ter. The maximum length of the control characters is
eight bits. If the length is less than eight bits then the
character must be right justified and the leading bits
be filled with zeros.
In uLAN mode this register contains the eight-bit sta-
tion address for recognition. In this mode only in-
coming address characters (i.e., characters with ad-
dress bit set) will be compared to these register. The
PCRF bit in the RECEIVE STATUS register will be
set when an Address or Control Character match
occurs.
6. ACR1DADDRESS/CONTROL CHARACTER REGISTER 1
ARC1DAddress/Control Character Register 1
271072–19
NOTE:
This register is identical in function to ACR0.
20