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參數資料
| 型號： | MR82510 |
| 廠商： | Intel Corp. |
| 英文描述： | ASYNCHRONOUS SERIAL CONTROLLER |
| 中文描述： | 異步串行控制器 |
| 文件頁數： | 31/40頁 |
| 文件大小： | 463K |
| 代理商： | MR82510 |
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M82510
26. TMSTDTIMER STATUS REGISTER
TMSTDTimer Status Register
271072–39
This register holds the status of the timers. Bits
TBEx and TAEx generate interrupts which are re-
flected in bit TIR of GSR. Bits GBS and GAS just
display the counting status, they do not generate in-
terrupts.
GBSDGate B StateD
This bit does not generate an
interrupt. It indicates the counting state of the soft-
ware gate of Timer B, as written through the TMCR
register.
0Dcounting disabled
1Dcounting enabled
GASDGateDA StateD
This bit does not generate
an interrupt. It reflects the state of the software gate
of Timer A, as written through the TMCR register.
0Dcounting disabled
1Dcounting enabled
TBExDTimer B ExpiredD
When Set generates an
interrupt through TIR bit of GSR. Indicates that Tim-
er B count has expired. This bit is set via the terminal
count pulse generated by the timer when it termi-
nates counting.
TAExDTimer A ExpiredD
Same as TBEx except it
refers to Timer A.
27. MSRDMODEM/I/O PINS REGISTER
MSRDModem/I/O Pins Status Register
271072–40
This register holds the status of the Modem input
pins (CTS, DCD, DSR, RI). It is the source of inter-
rupts (MSR 0–3) for the MIR bit of GSR. If any of the
above inputs change levels the appropriate bit in
MODEM STATUS is set. Reading MODEM STATUS
will clear the status bits.
DCDCDDCD ComplementD
Holds the comple-
ment of the DCD input pin if programmed as an input
in PMD.
DRICD
Holds the complement of the RI input pin if
programmed as an input in PMD.
DSRCDDSR ComplementD
Holds the complement
of the DSR input pin if configured as an input in
PMD.
CTSCDCTS ComplementD
Holds the complement
of the CTS pin.
DDCDDDelta DCDD
Indicates that the DCD input
pin has changed state since this register was last
read.
DRIDDelta RID
Indicates that there was a high-to-
low transition on the RI input pin since the register
was last read.
DDSRDDelta DSRD
Indicates that the DSR input
pin has changed state since this register was last
read.
DCTSDDelta CTSD
Indicates that the CTS input
pin has changed state since this register was last
read.
COMMAND REGISTERS
The command registers are write only; they are used
to trigger an operation by the device. Once the oper-
ation is started the register is automatically reset.
There is a device level register as well as four block
command registers. It is recommended that only one
command be issued during a write cycle.
31
相關PDF資料 |
PDF描述 |
|---|---|
| MR8251A | PROGRAMMABLE COMMUNICATION INTERFACE |
| MR851G | Axial Lead Fast Recovery Rectifiers |
| MR851RL | Axial Lead Fast Recovery Rectifiers |
| MR851RLG | Axial Lead Fast Recovery Rectifiers |
| MR852G | Axial Lead Fast Recovery Rectifiers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MR82510/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8251A | 制造商:Intel 功能描述: |
| MR8251A/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8254/B | 制造商:Rochester Electronics LLC 功能描述: |
| MR8254/R | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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