
M82510
3. TMDDTransmit Machine Mode Register
TMDDTransmit Machine Mode Register
271072–16
This register together with the Line Configure Regis-
ter defines the Tx machine mode of operation.
EEDDError Echo DisableD
Disables Echo of char-
acters received with errors (valid in echo mode
only).
CEDDControl Character Echo DisableD
Disables
Echo of characters recognized as control characters
(or address characters in uLAN mode). Valid in echo
mode only.
NBCLDNine-Bit LengthD
This bit, coupled with
LCR (CL0, CL1), selects Transmit/Receive charac-
ter length of nine bits. See Table 14.
TM1DTM0DTransmit ModeD
These bits select
one of three modes of control over the CTS and
RTS lines.
00DManual ModeD
In this mode the CPU has full
control of the Transmit operation. The CPU has to
explicitly enable/disable transmission, and activate/
check the RTS/CTS pins.
01DReserved
10DSemi-Automatic ModeD
In this mode the
M82510 transmits only when CTS input is active.
The M82510 activates the RTS output as long as
transmission is enabled.
11DAutomatic ModeD
In this mode the M82510
transmits only when CTS input is active. The RTS
output is activated only when transmission is en-
abled and there is more data to transmit.
SPFDSoftware Parity ForceD
This bit defines the
parity modes along with the PM0, PM1, and PM2 bits
of the LCR register. When software parity is enabled
the software must determine the parity bit through
the TxF register on transmission, or check the parity
bit in RxF upon reception. See Table 12.
SBL2DSBL1DStop Bit LengthD
These bits, to-
gether with the SBL0 bit of the LCR register define
the stop bit length. See Table 13.
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