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參數資料
| 型號： | P90CL301BFH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數： | 12/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301BFH |
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1996 Dec 11
12
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 14
Description of SYSCON bits
BIT
SYMBOL
DESCRIPTION
15
WDSC
Bus error Watchdog short cycle
. WDSC = 0 for normal mode; the bus error Watchdog
counts 2048 periods before activating the bus error sequence. WDSC = 1 for Bus error
Watchdog short cycle; the Watchdog counts 16 periods before activating the bus error
sequence.
Bus pull-up enable
. If BPE = 0, the Address and Data bus internal pull-ups are switched
off. If BPE = 1, the Address and Data bus internal pull-ups are switched on.
Invert bus size for chip select boot and mode of port P0 to P7
. CSBTX = 0 for normal
mode; bus size is defined by the pin BSIZE. If CSBTX = 1, the chip select boot is defined
by the inverted value of the pin BSIZE. The mode change should be executed from the
internal RAM or from a memory activated by any other chip select than CSBT. For further
details see also Section 6.3.
CPU Standby mode
. STBY = 0, for normal mode. STBY = 1, for Standby mode; only the
CPU clock is switched off, the peripheral clocks are still running (see Fig.4).
Prescaler for primary peripheral clock (FCLK) and the UART clock in mode 0
.
The CPU clock = CLK; FCLK =
1
divisor
×
CLK. See Table 15 for the divisor values.
Prescaler for secondary peripheral clock FCLK2
(derived from the primary peripheral
clock FCLK), used for the ADC; the maximum value of the FCLK2 clock is dependent on
the supply voltage V
DD
; see Section 19. If PCLK2 = 0, then FCLK is divided by 2;
if PCLK2 = 1, then FCLK is divided by 4.
If PDE = 0, then bits A22 to A19 are in normal operation; If PDE =1, then bits A22 to A19
are used as 8051 peripheral chip-select PCS3 to PCS0.
General purpose flag bit
; reset to a logic 0 after CPU reset.
For IM = 0, level 7 is loaded into the Status Register during interrupt processing to
prevent the CPU from being interrupted by another interrupt source. For IM = 1, the
current interrupt level is loaded into the Status Register allowing nested interrupts.
For WD = 0, the time-out for bus error detection is switched off. If the time-out is not
used, the Watchdog Timer can be used to stop a non-acknowledged bus transfer.
For WD = 1, the time-out for bus error detection is activated. If no DTACK has been sent
by the addressed device after 128
×
16 internal clock cycles the on-chip bus error signal
is activated.
FBC = 0, normal bus cycle; FBC = 1, fast bus cycle. An external read bus cycle can take
a minimum of 3 clock periods; the minimum write cycle is still 4 clock periods; in order to
get this access time DTACK should be asserted on time.
PD = 0, for normal mode; PD = 1, for Power-down mode (see Section 6.8).
IDL = 0, for normal mode; IDL = 1, for Idle mode (see Section 6.8).
DOFF = 0, for normal mode. DOFF = 1, for delay counter off; if set at wake-up from
Power-down the delay counter waiting period is skipped.
14
BPE
13
CSBTX
12
STBY
11, 7
and 6
10
PCLK3, PCLK1
and PCLK0
PCLK2
9
PDE
8
5
GF
IM
4
WD
3
FBC
2
1
0
PD
IDL
DOFF
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