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參數資料
| 型號： | P90CL301BFH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數： | 27/92頁 |
| 文件大?。?/td> | 526K |
| 代理商： | P90CL301BFH |
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1996 Dec 11
27
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
8
PORTS
For general purpose input/output operations the following
ports can be used:
16-bit bidirectional port lines P15 to P0 composed of two
8-bit ports PL (P7 to P0) and PH (P15 to P8)
8-bit port lines SP7 to SP0.
All port pins are multiplexed with other functions, but each
one can be individually switched to the port function by
setting the corresponding bit in the Port P Control Register
(PCON) for ‘port Pn’ and Port SP Control Register
(SPCON) for ‘port SPn’.
The port P7 to P0 is multiplexed with the data bus
D15 to D8 and is selected by the pin BSIZE.
Each port pin consists of a latch, an output driver with
pull-ups and an input buffer.
To use the port as input the port latch should be written
with a logic 1. This means only a weak pull-up is on and
can be overwritten by an external source logic 0.
When outputting a logic 1, a strong pull-up is turned on
only for 1 clock period, and then only the weak pull-up
maintains the HIGH level. In read mode, two different
internal addresses correspond to the port latch or the port
pin.The port values are read via register PPL and PPH.
After reset all ports are initialized as input, and the pins are
connected to the port latch with exception for the pin
NMIN/SP7 which is connected to the interrupt block.
8.1
Port P Control Register (PCON)
The port Pn is controlled via the Port P Control Register (PCON). The register PCON is only reset by an external reset,
and not by the RESET instruction. The port latches are accessed through the registers PRL and PRH.
Table 24
Port P Control Register (address FFFF 8503H)
Table 25
Description of PCON bits
8.1.1
P
ORT
P L
ATCHES
Table 26
Port P Latch least significant byte (PRL; address FFFF 8505H)
Table 27
Port Latches High most significant byte (PRH; address FFFF 8509H)
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
BIT
SYMBOL
DESCRIPTION
7 to 0
E15 to E8
If En = 0, then ‘port Pn’ is enabled; if En = 1, then the alternate function is enabled;
n = 8 to 15. The default value after reset is logic 0.
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
7
6
5
4
3
2
1
0
P15
P14
P13
P12
P11
P10
P9
P8
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