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參數(shù)資料
型號： P90CL301BFH
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Low voltage 16-bit microcontroller
中文描述： 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80
文件頁數(shù)： 76/92頁
文件大小： 526K
代理商： P90CL301BFH
1996 Dec 11
76
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
26 INSTRUCTION SET AND ADDRESSING MODES
The P90CL301BFH is completely code compatible with the 68000, which means that programs developed for the 68000
will run on the P90CL301BFH. This applies to both the source and object codes. The instruction set was designed to
minimize the number of mnemonics that the programmer has to remember. Following tables give an overview of the
instruction set and the different addressing modes.
Table 96
Instruction set; for Condition codes see notes 1 to 7
MNEMONIC
DESCRIPTION
OPERATION
CONDITION
CODES
X
N
Z
V
C
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL, ASR
B
CC
BCHG
Add Decimal with Extend
Add Binary
Add Address
Add Immediate
Add Quick
Add Extended
AND Logical
AND Immediate
Arithmetic Shift
Branch Conditionally
Test a Bit and Change
(Destination)
10
+ (Source)
10
+ X
→
Destination
(Destination) + (Source)
→
Destination
(Destination) + (Source)
→
Destination
(Destination) + Immediate Data
→
Destination
(Destination) + Immediate Data
→
Destination
(Destination) + (Source) + X
→
Destination
(Destination)
∧
(Source)
→
Destination
(Destination)
∧
Immediate Data
→
Destination
(Destination) Shifted by
<
count
> →
Destination
If CC then PC + d
→
PC
~(
<
bit number
>
) of Destination
→
Z
*
*
*
*
*
*
U
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
U
*
*
*
*
0
0
*
*
*
*
*
*
0
0
*
~(
<
bit number
>
) of Destination
→ <
bit number
>
of Destination
~(
<
bit number
>
) of Destination
→
Z
PC + d
→
PC
~(
<
bit number
>
) of Destination
→
Z
BCLR
BRA
BSET
Test a Bit and Clear
Branch Always
Test a Bit and Set
*
*
1
→ <
bit number
>
of Destination
PC
→
SP @
; PC + d
→
PC
~(
<
bit number
>
) of Destination
→
Z
If Dn
<
0 or Dn
>
(
<
source
>
) then TRAP
BSR
BTST
CHK
Branch to Subroutine
Test a Bit
Check Register against
Bounds
Clear an Operand
Compare
Compare Address
Compare Immediate
Compare Memory
Test Condition,
Decrement
&
Branch
Signed Divide
Unsigned Divide
Exclusive OR Logical
Exclusive OR Immediate
Exchange Register
*
*
U
U
U
CLR
CMP
CMPA
CMPI
CMPM
DB
cc
0
→
Destination
(Destination)
(Source)
(Destination)
(Source)
(Destination)
Immediate Data
(Destination)
(Source)
If (not CC) then Dn
1
→
Dn;
if Dn
≠
1 then PC + d
→
PC
(Destination) / (Source)
→
Destination
(Destination) / (Source)
→
Destination
(Destination)
⊕
(Source)
→
Destination
(Destination)
⊕
Immediate Data
→
Destination
Rx
Ry
0
*
*
*
*
1
*
*
*
*
0
*
*
*
*
0
*
*
*
*
DIVS
DIVU
EOR
EORI
EXG
*
*
*
*
*
*
*
*
*
*
0
0
0
0
0
0
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