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| 型號： | P90CL301BFH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數(shù)： | 63/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301BFH |
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1996 Dec 11
63
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
20 ADC CHARACTERISTICS
V
DD
= 2.7 to 3.6 V; V
ref(A)
= V
DDA
= V
DD
; V
SSA
= V
SS
; V
SS
= 0 V; FCLK2 = 250 kHz to 2 MHz; T
amb
=
40 to +85
°
C;
for ADC test conditions see note 1; all voltages with respect to V
SS
unless otherwise specified.
Notes
1.
2.
3.
4.
5.
ADC test conditions: V
DD
= 2.7 V, V
ref(A)
= 2.7 V, CLK = 20 MHz, FCLK2 = 2 MHz.
This resistor is switched off during Power-down mode and when the ADC is switched off (EADC = 0).
Parameter not measured in production, only verified on sampling basis.
See Fig.17 for specific FCLK2 range as function of V
DD
.
Absolute voltage error: the maximum difference between actual and ideal code transitions. Absolute voltage error
accounts for all deviations of an actual converter from an ideal converter.
Offset error: the difference between the actual and ideal input voltage corresponding to the first actual code transition.
Integral non-linearity: the maximum deviation between the edges of the steps of the transfer curve and the edges of
the steps of the ideal curve. The ideal step curve follows the line of least squares.
Differential non-linearity: the maximum deviation of the actual code width from the average code width.
Channel-to-channel matching: The difference between corresponding code transitions of actual characteristics taken
from different channels under the same temperature, voltage and frequency conditions.
6.
7.
8.
9.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DDA
V
ref(A)
V
SSA
V
IN(A)
I
DDA
I
DD(PD)(A)
analog supply voltage
analog reference voltage
analog ground
analog input voltage
supply current operating
analog supply current
Power-down mode
resistor between V
ref(A)
and V
SSA
note 2
analog input capacitance
input leakage current
ADC clock frequency;
sampling time
total conversion time
absolute voltage error
offset error
integral non-linearity
differential non-linearity
channel-to-channel matching
V
DD
0.2
V
DD
0.2
V
SS
0.2
0
150
0.1
V
DD
+ 0.2
V
DD
+ 0.2
V
SS
+ 0.2
V
ref(A)
250
5
V
V
V
V
μ
A
μ
A
V
DDA
= 3.0 V
V
DDA
= 3.0 V
R
Vref
C
IA
I
IA
FCLK2
t
ADS
t
ADC
A
e
OS
e
IL
e
DL
e
M
ctc
20
0.25
34
6
×
t
FCLK2
24
×
t
FCLK2
150
12
1
2
k
pF
μ
A
MHz
μ
s
μ
s
LSB
LSB
LSB
LSB
LSB
note 3
V
DDA
= 3.0 V
V
DDA
= 2.7 V; note 4
note 1 and 5
note 1 and 6
note 1 and 7
note 1 and 8
note 3 and 9
1
1
1
1
1
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