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參數(shù)資料
型號(hào)： P90CL301BFH
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： Low voltage 16-bit microcontroller
中文描述： 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80
文件頁(yè)數(shù)： 42/92頁(yè)
文件大小： 526K
代理商： P90CL301BFH
1996 Dec 11
42
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.3.1
R
ECEPTION
C
ONTROL
R
EGISTER
(UQRC)
In order to keep the bit unchanged when writing to the control register, it is recommended to write a logic 1 when it can
only be reset, and to write a logic 0 when it can only be set. After peripheral reset all bits are set to a logic 0.
Table 55
Reception Control Register (address FFFF 8B00H)
Notes
1.
2.
CPU. R: the CPU can reset this bit. S: the CPU can set this bit.
QUEUE. R: the queue controller can reset this bit. S: the queue controller can set this bit.
Table 56
Description of UQRC bits
ACTION OF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REN
RME
RIE
ROE
ROF
RAR
RHLT
RSTF
CPU
(1)
QUEUE
(2)
S/R
S/R
S/R
S/R
R
S
S/R
S/R
S
R
BIT
SYMBOL
DESCRIPTION
7
REN
Receive queue enable
. This bit enables the queue controller. It connects the reception
data buffer SBUF0 to the queue controller. It should be set before activating the RSTF bit.
When it is reset SBUF0 can be accessed directly by the CPU. REN = 0 means receive
queue disable. Received byte can be read directly from SBUF0. REN = 1 means receive
queue enable: The transfers from the SBUF0 to the RAM can be activated by setting the
bit RSTF.
Reception match enable
. If it is set each received byte is compared with the content of
the UART Queue Receive Match register (UQRM) and if their value match the receive
interrupt flag RIF is set. RME = 0 means match function disabled. RME = 1 means match
function enabled.
Reception interrupt enable
. When this bit is set, each time a byte is received the receive
interrupt flag RIF is set. If it is not set, an interrupt is only generated at the end of the
frame. RIE = 0 means no interrupt after the reception of each byte, only at the end of the
frame. RIE = 1 means interrupt after the reception of each byte.
Reception overflow enable
. When this bit is set, the RSTF bit is not reset when the
reception buffer size reached 0, setting the RIF flag, so the reception of further bytes is
allowed. The bit ROF is not set because RSTF stays set. This bit can be set in conjunction
of RAR to implement a circular buffer. ROE = 0 means no overflow enable. ROE = 1
means overflow enable.
Reception overflow flag
. This flag is set by the queue controller, when a character is
received with the RSTF flag reset and REN set. This event can occur after the end of
reception of a frame, and if the CPU had no time to unload the RAM and set RSTF.
ROF = 0 means no overflow detection. ROF = 1 means overflow.
6
RME
5
RIE
4
ROE
3
ROF
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