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參數資料
| 型號： | P90CL301BFH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數： | 40/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301BFH |
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1996 Dec 11
40
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.2
Baud rate generator
A dedicated baud rate generator is directly connected to
the UART0. For the UART1 this clock can be divided by
1 or 4 as a function of the bit BDIV in the BCON control
register.
The baud rate generator consists of a 16-bit timer, two
8-bit registers BREGL (least significant byte) and BREGH
(most significant byte) to store the 16-bit reload value, and
a control register BCON.
When an overflow occurs the timer is reloaded with the
contents of the registers BREGH, BREGL.
The timer is clocked by the peripheral clock. The baud
rates for UART0 and UART1 in Mode 1 and 3 are
determined by the timer overflow rate as follows
(FCLK is in Hz):
BGCLK0
16x 65536
BREG
–
)
(
)
----------------------FCLK
=
BGCLK1
16
65536
BREG
–
(
)
x4
BDIV
×
--------------------------------FCLK
=
12.2.1
UART B
AUD
R
ATE
C
ONTROL
R
EGISTER
(BCON)
The default value after a CPU reset for all bits of BCON is a logic 0.
Table 52
UART Baud Rate Control Register (address FFFF 860FH)
Table 53
Description of BCON bits
7
6
5
4
3
2
1
0
BST
BDIV
BIT
SYMBOL
BST
DESCRIPTION
7 to 2
1
Reserved.
BST = 0, stop timer; BST = 1, start timer increment after loading of timer register with
the reload register value.
BDIV = 0, UART1 baud rate not divided; BDIV = 1, UART1 baud rate divided by 4.
0
BDIV
12.3
UART queue
The UART queue performs the sending and receiving of a
frame of bytes of variable length through the UART without
the support of the CPU. Only the UART0 has a frame
buffer located at the lower 256 bytes section of the internal
RAM. A controller ensures the sequencing of the transfers
between the RAM and the UART and generates interrupts
to the CPU. This UART queue can be used for
transmission and reception simultaneously or for only one
of the two modes.
The RAM can be accessed by the CPU any time.
The queue controller accesses the RAM either in read
mode for the transmission or in write mode for the
reception. When the queue controller accesses the RAM,
the CPU waits for the end of the access cycle (maximum 4
CLK clocks). The RAM space can be partitioned in one or
several buffers for transmission or reception or for normal
data storage. The maximum size of a buffer is limited to
256 bytes. In addition to these buffers the queue consists
of a set of control and data registers:
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