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參數資料
| 型號： | P90CL301BFH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數： | 22/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301BFH |
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1996 Dec 11
22
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
7.3
Processing states and exception processing
The P90CL301BFH operates with a maximum internal
clock frequency of 27 MHz down to static operation. Each
clock cycle is divided into 2 states. A non-access machine
cycle has 3 clock cycles or 6 states (S0 to S5). A minimum
bus cycle normally consists of 3 clock cycles (6 states).
When DTACK is not asserted, indicating that data transfer
has not yet been terminated, wait states (WS) are inserted
in multiples of 2.
The CPU is always in one of the four processing states:
Normal
Exception
Halt
Stopped.
The Normal processing state is associated with instruction
execution; the memory references fetch instructions or
load/save results. A special case of the Normal state is the
Stopped state which is entered by the processor when a
STOP instruction is executed. In this state the CPU does
not make any further memory references.
The Exception state is associated with interrupts, trap
instruction, tracing and other exceptional conditions.
The exception may be generated internally by an
instruction or by any unusual condition arising during the
execution of an instruction. Externally, exception
processing can be forced by an interrupt or by reset.
The halted processing state is an indication of a
catastrophic hardware failure. For example, if during
exception processing of a bus error another bus error
occurs, the CPU assumes that the system is unusable and
halts. Only an external reset can restart a halted
processor. Note that a CPU in the stopped state is not in
the halted state or vice versa.
The Supervisor can work in the User or Supervisor state
determined by the state of bit S in the Status Register.
Accesses to the on-chip peripherals are achieved in the
Supervisor state.
All exception processing is performed in the Supervisor
state once the current contents of the Status Register has
been saved. Then the exception vector number is
determined and copies of the Status Register, the program
counter and the format/vector number are saved on the
Supervisor stack using the Supervisor Stack Pointer
(SSP). Finally the contents of the exception vector location
is fetched and loaded into the Program Counter (PC).
7.3.1
R
EFERENCE CLASSIFICATION
When the processor makes a reference, it classifies the
kind of reference being made, using the encoding of the
three function code internal lines. This allows external
translation of addresses, control of access, and
differentiation of special processor states, such as
interrupt acknowledge. Table 21 shows the classification
of references.
Table 21
Reference classification
7.3.2
E
XCEPTION VECTORS
Exception vectors are memory locations from where the
CPU fetches the address of a routine that will handle that
exception. All exception vectors are 2 words long, except
for the reset vector which consists of 4 words, containing
the PC and the SSP. All exception vectors are in the
Supervisor Data space.
A vector number is an 8-bit number which, multiplied by 4,
gives the address of an exception vector. Vector numbers
are generated internally. The memory map for the
exception vectors is shown in the Table 22.
FUNCTION CODE
REFERENCE CLASS
FC2
FC1
FC0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
unassigned
User Data
User Program
unassigned
unassigned
Supervisor Data
Supervisor Program
interrupt acknowledge
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