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參數資料
| 型號： | P90CL301BFH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數： | 43/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301BFH |
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1996 Dec 11
43
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.3.2
T
RANSMISSION
C
ONTROL
R
EGISTER AND
I
NTERRUPT
F
LAGS
(UQTC)
Table 57
Transmission Control Register and Interrupt Flags (address FFFF 8B01H)
Notes
1.
2.
CPU. R: the CPU can reset this bit. S: the CPU can set this bit.
QUEUE. R: the queue controller can reset this bit. S: the queue controller can set this bit.
Table 58
Description of UQTC bits
2
RAR
Reception address reset
. If this flag is set, when the buffer size has been decremented
to zero, the reception address is reset. This way a circular reception buffer can be located
at address 0. RAR = 0 means no reset of reception address. RAR = 1 means reset of
reception address.
Reception halt
. This bit is set by the CPU to interrupt the reception of the frame. The byte
currently received by the UART will be stored in the buffer, but the next bytes will be lost
until the CPU reset the bit RHLT. In order to stop all activity in the UART it is preferable to
reset the bit REN reception enable of the register SCON0. RHLT = 0 means reception not
halted. RHLT = 1 means reception halted.
Reception start flag
. This bit is set by the CPU to enable the reception of a frame
through the UART and it is reset automatically by the queue controller at the end of
reception. When RHLT is set this bit stays set. When REN is reset, this bit is reset.
RSTF = 0 means reception not started or ended. RSTF = 1 means reception started and
in progress.
1
RHLT
0
RSTF
ACTION OF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TIF
RIF
reserved
TIWF
S/R
TEN
TIE
THLT
TSTF
CPU
(1)
QUEUE
(2)
R
S
R
S
S/R
S/R
S/R
S
R
BIT
SYMBOL
DESCRIPTION
7
TIF
Transmission interrupt flag
. This flag is set either at the end of the transmission buffer
or at the transmission of each byte if TIE is set. The TIF flag should be reset by the CPU in
the exception routine in order to detect further interrupts as they are edge detected for
LOW-to-HIGH transitions.
Reception interrupt flag
. This flag is set either at the end of the reception buffer or during
a character match if RME is set or at the reception of each byte if RIE is set. The RIF flag
should be reset by the CPU in the exception routine in order to detect further interrupts as
they are edge detected for LOW-to-HIGH transitions.
Reserved.
Transmission interrupt waiting
. TIWF = 0
(1)
means queue controller is not waiting for
UART transmit interrupt.TIWF = 1 means queue controller is waiting for UART transmit
interrupt.
Transmission queue enable
. TEN = 0
(1)
means transmission queue disable.
Transmitted byte can be written directly into SBUF0. TEN = 1 means transmission queue
enable; the transfers from the RAM to SBUF0 can be activated by setting the bit TSTF.
6
RIF
5
4
TIWF
3
TEN
BIT
SYMBOL
DESCRIPTION
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