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參數資料
| 型號： | P90CL301BFH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數： | 45/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301BFH |
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1996 Dec 11
45
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.3.4
UART
QUEUE OPERATION
: T
RANSMISSION
The UART queue transmit operation is as follows:
1.
The UART control register is initialized for a certain
transmission mode (0, 1, 2 and 3) and the baud rate
generator loaded for a defined baud rate.
2.
The CPU loads the data to be transmitted (for example
80 characters) at successive addresses of the internal
RAM starting at a certain base address (for example
FFFF 9010H). Then it writes the buffer start address
and the buffer size in the pointer registers, and
initializes the control register.
3.
The queue controller reads the byte at the address
pointed by the address register and writes it to the
transmit data buffer of the UART and the buffer size
register is decremented, the address register is
incremented pointing to the next byte in the buffer.
The transmission starts. The controller waits for the
end of transmission, then compares the buffer size
value to zero, if they are not equal the same operation
is repeated automatically.
4.
If the buffer size is zero the transmit interrupt flag TIF
is set issuing an interrupt to the CPU.The interrupt
routine should reset TIF and can reload the buffer with
other values.
5.
Before checking the buffer size value, the halt bit THLT
is tested and if it is set the controller enters a
transmission wait state.
Table 60
Transmission routine
12.3.5
UART
QUEUE OPERATION
: R
ECEPTION
The UART queue reception operation is as follows:
The UART control register is initialized for a certain
reception mode (Mode 0, 1, 2 and 3) and the baud rate
generator loaded for a defined baud rate.
The CPU writes the buffer start address and the buffer size
in the data registers, and the control register. Several
modes can be used:
move.b #$50,UQTS
move.b #$10,UQTA
bset
TEN,UQTC; ;Enable transmission queue
bset
STF,UQTC;
;Start transmission.
;buffer size
;buffer start address
12.3.5.1
Mode 0: Normal reception buffer.
We want to receive 80 characters, store then in a buffer
starting at the address FFFF 9020H and generate an
interrupt. The CPU is able to down-load the 80 characters,
before the reception of any further character.
After reception of the first character the queue controller
reads the data reception register SBUF0 and transfers it’s
contents into the buffer at the address of the UQRA
register, at the same time the buffer size register UQRS is
decremented, the address register UQRA is incremented
to point to the next byte. If the buffer size is not equal to
zero the same operation is repeated automatically for the
next byte to be transmitted.
If the buffer size is zero the receive interrupt flag RIF is set
issuing an interrupt to the CPU. The interrupt routine
should reset RIF and can read the content of the buffer and
re-initialize the control registers.
Table 61
Reception routine
Table 62
Interrupt routine
move.b #$50, UQRS
move.
#$20, UQRA
bset
REN, UQRC
bset
RSTF, UQRC
;set buffer size
;set buffer start address
;Enable queue controller
;Start reception.
move.b
move.b
move.l
move.l
#$BE,UQTC
#$28,d0
#$FFFF9020,a0
#$00008000,a1
;reset RIF bit
;buffer size in words
;buffer start address
;external memory
start address
;loop
L1
dbne
d0,L1
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