
1996 Dec 11
84
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 106
Conditional instruction clock periods
Note
1.
Add effective address calculation time.
Table 107
JMP, JSR, LEA, PEA, MOVEM instruction clock periods
n = number of registers to move.
Table 108
Multi-precision Instruction Clock Periods
INSTRUCTION
DISPLAY
TRAP OR BRANCH
TAKEN
NOT TAKEN
Bcc
Byte
Word
Byte
Word
Byte
Word
cc True
cc False
13 (1/0)
14 (2/0)
13 (1/0)
14 (2/0)
21 (1/2)
22 (2/2)
13 (1/0)
14 (2/0)
BRA
BSR
DBcc
14 (2/0)
17 (3/2)
19 (1/0)
(1)
10 (1/0)
17 (2/0)
70 (3/4)
(1)
55 (3/4)
CHK
TRAPV
INSTRUCTION SIZE
(An)
(An)+
(An)
d(An)
d(An, Xi)
xxx.S
xxx.L
d(PC)
d(PC, Xi)
JMP
JSR
LEA
PEA
MOVEM
M
→
R
Word 26+7n
7 (1/0)
18 (1/2)
7 (1/0)
18 (1/2)
26+7n
(2+n/0)
26+11n
(2+2n/0)
14 (2/0)
25 (2/2)
14 (2/0)
25 (2/2)
30+7n
(3+n/0)
30+11n
(3+2n/0)
27+7n
(3/n)
27+11n
(3/2n)
17 (2/0)
28 (2/2)
17 (2/0)
28 (2/2)
33+7n
(3+n/0)
33+11n
(3+2n/0)
30+7n
(3/n)
30+11n
(3/2n)
14 (2/0)
25 (2/2)
14 (2/0)
25 (2/2)
30+7n
(3+n/0)
30+11n
(3+2n/0)
27+7n
(3/n)
27+11n
(3/2n)
18 (3/0)
28 (2/2)
18 (3/0)
28 (2/2)
34+7n
(4+n/0)
34+11n
(4+2n/0)
31+7n
(4/n)
31+11n
(4/2n)
14 (2/0)
25 (2/2)
14 (2/0)
25 (2/2)
30+7n
(3+n/0)
30+11n
(3+2n/0)
17 (2/0)
28 (2/2)
17 (2/0)
28 (2/2)
33+7n
(3+n/0)
33+11n
(3+2n/0)
(2+n/0)
26+11n
(2+2n/0)
Long
MOVEM
R
→
M
Word 23+7n
(2/n)
23+11n
(2/2n)
23+7n
(2/n)
23+11n
(2/2n)
Long
INSTRUCTION
SIZE
op Dn, An
op M, M
ADDX
Byte, Word
Long
Byte, Word
Long
Byte, Word
Long
Byte
Byte
7 (1/0)
7 (1/0)
7 (1/0)
7 (1/0)
10 (1/0)
10 (1/0)
28 (3/1)
40 (5/2)
18 (3/0)
26 (5/0)
28 (3/1)
40 (5/2)
31 (3/1)
31 (3/1)
CMPM
SUBX
ABCD
SBCD