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參數資料
| 型號： | P90CL301BFH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數： | 52/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301BFH |
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1996 Dec 11
52
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
13 PULSE WIDTH MODULATION (PWM) OUTPUTS
Two Pulse Width Modulation outputs are provided on the
P90CL301. These channels output pulses of
programmable length and interval. The repetition
frequency is defined by an 8-bit prescaler PWMP, which
generates the clock for the counter. The 8-bit counter
counts modulo 255 (from 0 to 254 inclusive).
The prescaler and counter are used for the two channel
outputs. The value of the 8-bit counter is compared to the
content of the registers PWM0 (resp. PWM1) for the
channel output PWM0 (resp. PWM1). Provided the
content of this register is greater than the counter value,
the output of PWM0 (resp. PWM1) is set LOW. If the
content of this register is equal to, or less than the counter
value, the output will stay high. The pulse width ratio is
therefore defined by the content of the register PWM0
(respectively PWM1).
The pulse width ratio is in the range of 0 to
255
255
and may
be programmed in increments of
1
255
.
The repetition frequency:
; for FCLK in Hz.
When using a peripheral clock of 6 MHz for example, the
above formula gives a repetition frequency range of
23 kHz to 91 Hz.
By loading the PWM0 (resp. PWM1) with either 00H or
FFH, the PWM0 output can be retained at a constant HIGH
or LOW level respectively. When loading FFH to the
PWM0 (respectively PWM1) register, the 8-bit counter will
never actually reach this value.
f
PWM
PWMP
1
+
(
)
255
×
------------------FCLK
=
13.1
Prescaler PWM Register (PWMP)
Table 82
Prescaler PWM Register (address FFFF 8801H)
Table 83
Description of PWMP bits
13.2
PWM Data Registers (PWM0 and PWM1)
Table 84
PWM Data Registers PWM0 and PWM1
Table 85
Description of PWM0 and PWM1 bits; n = 0 to 1
7
6
5
4
3
2
1
0
PWMP.7
PWMP.6
PWMP.5
PWMP.4
PWMP.3
PWMP.2
PWMP.1
PWMP.0
BIT
SYMBOL
DESCRIPTION
7 to 0
PWMP.7 to PWMP.0
Prescaler division factor = (PWMP + 1).
ADDRESS
REGISTER
7
6
5
4
3
2
1
0
FFFF 8803H
FFFF 8805H
PWM0
PWM1
PWM0.7
PWM1.7
PWM0.6
PWM1.6
PWM0.5
PWM1.5
PWM0.4
PWM1.4
PWM0.3
PWM1.3
PWM0.2
PWM1.2
PWM0.1
PWM1.1
PWM0.0
PWM1.0
BIT
SYMBOL
DESCRIPTION
7 to 0
PWMn.7 to PWMn.0
Pulse width ratio. LOW/HIGH ratio of PWMn signals
PWMn
–
255
)
------------------PWMn
=
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