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參數資料
| 型號： | P90CL301BFH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數： | 46/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301BFH |
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1996 Dec 11
46
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.3.5.2
Mode 1: Special termination character match.
Suppose that we want to generate an interrupt after the
reception of a Carriage Return character, we load in the
reception match register the value 0DH, to guarantee that
the buffer does not overflow if the buffer size is limited to
80 characters. The buffer is located in RAM at the address
FFFF 9050H.
The same operations as described before are performed
but in addition each received characters compared with
the character Carriage Return and if they match the
receive interrupt flag RIF is set, RSTF is reset and the
reception queue is stopped.
Table 63
Mode 1 routine
Note
1.
All these control bits can be set at the same time.
12.3.5.3
Mode 2: Linear buffer with continuous
reception.
If we want to continue to receive characters in the buffer
after the end of the buffer and the setting of RIF:
In this case RSTF is not reset at the end of the buffer, but
the CPU will receive an interrupt (RIF = 1) when the size
register UQRS equals zero.
Table 64
Mode 2 routine
Note
1.
All these control bits can be set at the same time.
move.b #$50,UQRS
move.b #$50,UQRA
move.b #$0d,UQRM
bset
REN,UQRC
bset
RME,UQRC
bset
RSTF,UQRC
; buffer size
; buffer start address
; set match character
; enable queue
; reception match enable
; start reception (note 1)
move.b #$50,UQRS
move.b #$50,UQRA
bset
REN,UQRC
bset
ROE,UQRC
bset
RSTF,UQRC
; buffer size
; buffer start address
; enable queue
; reception overflow enable
; start reception (note 1)
12.3.5.4
Mode 3: Circular buffer with interrupt.
If we want to implement a circular buffer which generates
an interrupt each time the size register is equal to 0, the
UQRA address register is reset and points to the beginning
of the RAM.
Table 65
Mode 3 routine
Note
1.
All these control bits can be set at the same time.
12.3.6
UART
QUEUE OPERATION
: R
ECEPTION HALT
Before to check the buffer size value, the halt bit HLTR0 is
tested and if it is set the controller enters a reception wait
state.
12.3.7
UART
QUEUE OPERATION
: E
MULATION
When the pin PHALT (on the emulation package) is
asserted LOW, the queue is halted the same way as when
THLT and RHLT are set. The queue operation is continued
when the pin PHALT is released HIGH.
move.b #$50,UQRS
move.b #$00,UQRA
bset
REN,UQRC
bset
RAR,UQRC
bset
RSTF,UQRC
; buffer size
; buffer start address
; enable queue
; reception reset address
; start reception (note 1)
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