
1996 Dec 11
30
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
n
data input
MGD783
external
pull-up
pin
Fig.9 Port schematics (continued from Fig.8).
handbook, halfpage
n
p
data input
MGD785
pin
VDD
handbook, halfpage
n
power
down
MGD786
pin
VDD
RVref
a. Open-drain port.
b. 3-state port.
c. AREF input.
9
8051 PERIPHERAL BUS
The P90CL301BFH can also directly access the peripheral
circuits which are compatible with the 8048/8051 bus.
When the CPU accesses locations located in the
64 kbytes peripheral space, an Address/Data multiplexed
access is generated using the AD0 to AD7 lines, the
non-multiplexed A8 to A15 lines and the 8051 control bus
(ALE, RD, WR). In order to use these three signals the
alternate mode of the CS5 to CS3 should be set. A 8051
bus access is performed by addressing a byte in the
8001 0000H to 8001 FFFFH range.
To reduce the number of interface circuits, the address
lines A22 to A19 can be used as peripheral chip-select
outputsPCS0 to PCS3. This is done by setting the PDE bit
(SYSCON) to a logic 1;
PCS0 selects memory range 0 kbytes to 16 kbytes
PCS1 selects memory range 16 kbytes to 32 kbytes
PCS2 selects memory range 32 kbytes to 48 kbytes
PCS3 selects memory range 48 kbytes to 64 kbytes.
The timing of the peripheral bus is fixed and compatible
with the 8051 peripheral circuits.