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參數資料
| 型號： | P90CL301BFH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 16-bit microcontroller |
| 中文描述： | 16-BIT, 27.02 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數： | 31/92頁 |
| 文件大小： | 526K |
| 代理商： | P90CL301BFH |
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1996 Dec 11
31
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
10 ON-CHIP PERIPHERAL FUNCTIONS
The P90CL301BFH integrates a number of peripheral
functions connected to the internal bus:
Timers (T0 and T1)
Watchdog
2 UART interfaces with one UART queue controller
using the internal RAM as data buffers.
I
2
C-bus interface
PWM (Pulse Width Modulation)
ADC (Analog-to-Digital Converter).
These functions are accessible as memory locations on a
byte or word basis. The access is auto-acknowledged by
on-chip logic. The on-chip peripheral functions can
generate auto-vectored interrupts to the CPU using the
second vector table (vectors 57 to 63).
10.1
Peripheral interrupt control
The timers T0 and T1, I
2
C-bus, UART and ADC use a
common set of Peripheral Interrupt Control Registers
(PICRn; n = 0 to 3). These registers are accessible from
the CPU and contain the Interrupt Priority Level flags
IPL2 to IPL0 as well as the Pending Interrupt flags PIR.
PIR is set when a valid interrupt request has been
detected. It is automatically reset by the interrupt
acknowledge cycle from the CPU. The PIR flag can be
reset by software.
The Interrupt Priority Level code ‘111B’ represents the
interrupt with the highest priority. The code ‘000B’ inhibits
the interrupt.
10.1.1
T
IMER
I
NTERRUPT
R
EGISTER
(PICR0)
On timer overflow or on channel capture/match the pending interrupt request flag PIRTn is set. If the interrupt priority
level is different from zero, the timer activates an interrupt to the CPU.
Table 32
Timer Interrupt Register (address FFFF 8701H)
Table 33
Description of PICR0 bits
7
6
5
4
3
2
1
0
PIRT1
IPLT1.2
IPLT1.1
IPLT1.0
PIRT0
IPLT0.2
IPLT0.1
IPLT0.0
BIT
SYMBOL
DESCRIPTION
7
PIRT1
pending interrupt for timer T1
interrupt priority level for timer T1
pending interrupt for timer T0
interrupt priority level for timer T0
6 to 4
3
2 to 0
IPLT1.2 to IPLT1.0
PIRT0
IPLT0.2 to IPLT0.0
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